I have some conflicting requirements on the design I’m working on. I need to use an external PLL to generate clocks of various rates (determined at run-time) that are locked to a clock that is an input to my board. I need to clean up any jitter on this input reference. I’ve seen some PLLs that are targeted towards jitter attenuation but I thought such devices suffer longer lock times. I can’t afford to wait a long time for lock because that effectively means input data is thrown away in my system. Has anyone done any designs like this? What’s your thought process for picking such a PLL?
I’ve done some work in this area. In my experience, deciding between the tradeoff of jitter attenuation vs. lock-time requires good knowledge of how much jitter the input reference will have.
However, on the products I designed, I actually didn’t know how much jitter to expect nor did I have a good way to find out. So the approach I took was to use a PLL whose loop bandwidth was programmable. Lower loop bandwidth = better jitter attenuation (but longer lock time). So this let me play with the tradeoff in the lab and in some customer settings.
In other words, my suggestion is to use a part that lets you defer making the choice until a point in the future when you have more information.
Silicon Labs has a bunch of PLLs that would work, like the Si5374. Here’s a reference design for that part:
https://upverter.com/anandh/3beda9c266261f6a/Si5374-PLL-Reference-Design/
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