Constraint: U459 hole closer than 0.25mm to PTH

I am confounded. I don’t know what this constraint means or how to fix it.

I forked a good design (to keep a copy of the A version we sent to the PCB maker), and then am using this B version (from the fork) for enhancements, and for implementing fixes should we find bugs in the first PCB. I made a few changes in the B version in the corners, none of which involved the components called out in the constraints.

U459 is a 14 pin DIP package with pin-through-hole (PTH) leads. We have a bunch of these ICs on the PCB and all have the same constraint. The A version had no problems.

Any ideas?

I have stumbled across additional clues as to what might be causing the above. The message I get above (“U459 hole closer than 0.25mm to PTH”, but is found in 38 places for the Uxxx components) is somehow related to non-plated holes I put in the corners of the boards. These non-plated holes will be for screws, for mounting the PCB. If I remove the 4 non-plated holes, the 38 constraints disappear. The non-plated hole has none for a Net Attachment.

I have altered the pour outline in one corner so that there is no pour layer (either top or bottom) where I have the hole. I then added a non-plated hole to that unpoured area. I still get the constraint.

When does the constraint appear? When I add the hole, I do not get the constraint. When I log off upverter and come back later to logon, then the constraint is there.

I have put non-plated holes in the 4 corners of another PCB and did not have this issue. The parameters I selected for the non-plated hole on this PCB are the same as on the PCB that worked. So I am a bit perplexed.